1. Field of the Invention
The present invention relates to a resin seal semiconductor package accommodating a semiconductor component and a manufacturing method of the same. In particular, the invention relates to the resin seal semiconductor package which can achieve a high performance and a high reliability as well as reduction in size, and also relates to the manufacturing method of the same.
2. Description of the Related Art
Semiconductor packages are well-known containers for accommodating semiconductor components. Two kinds of materials, i.e., ceramics and resin, are generally known as the material of the semiconductor packages. Of these materials, the semiconductor packages made of resin have been broadly used as commercial packages because of low material costs and high mass-productivity. A conventional example of the package made of resin, i.e., a so called resin seal semiconductor package will be described below.
FIG. 95 is a perspective view partially in section showing an example of the conventional resin seal semiconductor package. Referring to FIG. 95, a semiconductor chip 103 on which elements are formed is disposed on a die pad 107 made of Fe--Ni alloy or the like. Bonding pads 104 which function as external I/O electrodes are formed on a main surface of the semiconductor chip 103. Around the die pad 107, there are disposed internal leads 105 and external leads 102 for electrical connection with electrodes of external equipments.
The bonding pads 104 and the internal leads 105 are electrically connected together by bonding wires 106 made of gold (Au) or the like. Thereby, elements formed on the semiconductor chip 103 and the external equipments are electrically connected. The die pad 107, semiconductor chip 103 and internal leads 105 are covered with seal resin 101.
The above resin seal semiconductor package suffers from following problems because of the structure described above. The conventional structure requires the bonding wires 106, internal leads 105 and external leads 102 for electrically connecting the elements and external equipments. Regions in which the bonding wires 106 and internal leads 105 are formed cause a problem.
Since the regions for the bonding wires 106 and internal leads 105 are required around the semiconductor chip 103, the seal resin 101 has a width larger by about 1 mm than a width of the semiconductor chip 103. This impedes reduction of the package size.
Further, connections (i.e., bonding wires 106, internal leads 105 and external leads 102) for the external equipments are relatively long, which deteriorates electrical performance because of an increase of the impedance component.
Three improvements aimed at reduction of the package sizes and improvement of the electrical performance have been proposed for overcoming the above problems. These improvements will be described below with reference to FIGS. 96-99.
FIG. 96 is a cross section showing a resin seal semiconductor package of a first improvement disclosed in Japanese Patent Laying-Open No. 3-104141 (1991). Referring to FIG. 96, bonding pads 114 are formed on a main surface of a semiconductor chip 113. Protruded electrodes 112 to be electrically connected to external equipments are formed on the bonding pads 114. The protruded electrodes 112 may be made of solder (Pb/Sn) or other electrically conductive material plated with solder. Tip ends of the protruded electrodes 112 are protruded externally through a seal resin 111 covering the semiconductor chip 113.
Owing to the structures described above, the resin seal semiconductor package of the first improvement comes to have a size nearly equal to that of the semiconductor chip 113, and thus can be smaller than conventional semiconductor packages. Further, the connections (i.e., protruded electrodes 12) for external equipments can be made shorter than the conventional connections, so that the electrical property can be improved.
A second improvement will now be described below with reference to FIGS. 97 and 98. FIG. 97 is fragmentary cross section showing a resin seal semiconductor package of the second improvement disclosed in Japanese Patent Laying-Open No. 4-207046 (1992). In FIG. 98 A to D are perspective views partially in section showing different steps in a process of manufacturing the resin seal semiconductor package in FIG. 97.
Referring first to FIG. 97, a bonding pad 124 is formed on a main surface of a semiconductor chip 123. A protection film 126 is formed on the main surface of the semiconductor chip 123. The protection film 126 has an opening which is located on a portion of a surface of the bonding pad 124. The protection film 126 and the semiconductor chip 123 form a semiconductor element 125.
A seal resin 121 is formed over the protection film 126. The seal resin 121 is provided with an opening 121a located above the bonding bad 124. A protruded electrode 122 protruded from the surface of the seal resin 121 is formed in the opening 121a and is located on the bonding pad 124. Metal of a low melting point or electrically conductive resin is disclosed as the material of protruded electrode 122.
A method of manufacturing the resin seal semiconductor package of the second improvement thus structured will be described below with reference to FIGS. 98A-98D. Referring first to FIG. 98A, a plurality of bonding pads 124 are formed at predetermined positions on the main surface of the semiconductor chip 123. The protection film (not shown in FIGS. 98A-98D) is formed such that the openings thereof are located on portions of the surfaces of the bonding pads 124. In this manner, the semiconductor element 125 is formed.
In FIG. 98B, the seal resin 121 is formed on the main surface of the semiconductor element 125. Then, as shown in FIG. 98C, the openings 121a extending to the bonding pads 124 are formed at portions of the seal resin 121 located above the bonding pads 124. As shown in FIG. 98D, the openings 121a are filled with conductive material to form the protruded electrodes 122.
Owing to the structures described above, the second improvement can reduce the size of the package and improve the electrical performance similarly to the first improvement.
A third improvement will be described below with reference to FIG. 99, which is a cross section of a resin seal semiconductor package disclosed in Japanese Patent Laying-Open No. 4-139848 (1992). In FIG. 99, an interconnection layer 135 and bonding pads 134 are formed on a surface of a semiconductor chip 133.
The interconnection layer 135 is covered with a protection film 136 having openings located on portions of surfaces of the bonding pads 134. Bonding pads 134 are connected to columnar electrodes 132 formed thereon. The semiconductor chip 133 is sealed with a seal resin 131 which exposes only top surfaces of the electrodes 132.
Owing to the above structures, the third improvement can reduce the size of the semiconductor package and improve the electrical performance similarly to the first and second improvements.
As described above, the resin seal semiconductor packages of the first to third improvements have such advantages that the size of the semiconductor packages can be reduced and the electrical performance can be improved, but they respectively have following problems, which will be described below with reference to FIGS. 100-103.
First, the problem of the first improvement will be described below with reference to FIGS. 100 and 101. FIG. 100 is a cross section schematically showing a problem of the protruded electrode 112 made only of solder. FIGS. 101A and 101B are cross sections showing different steps for connecting the semiconductor package to the interconnection on a printed board in the case where a solder 115 is plated on the top surface of the protruded electrode 112.
Referring to FIG. 100, if the protruded electrode 112 is formed only of a single layer of solder, there arises a problem when connecting the protruded electrode 112 to the interconnection layer on the printed board (not shown). In a general manner of connecting the protruded electrode 112 to the interconnection layer on the printed board, solder in the form a paste (will be referred to as "solder paste") is provided on the interconnection layer on the printed board, and the protruded electrode 112 is welded to the solder paste.
If the protruded electrode 112 is formed only of the single layer of solder as described above, the protruded electrode itself melts, so that an electrode on the printed board is bonded to the protruded electrode 112. Thereby, a gap 116 may be formed at an interface between the seal resin 111 and the protruded electrode 112 as shown in FIG. 100. This causes such problems that the protruded electrode 112 is liable to be detached and moisture may enter the gap 116, resulting in reduction of reliability of the semiconductor package.
Another problem may be caused in the case where the solder plating layer 115 is formed over the top surface of the protruded electrode 112, as will be described below. Referring to FIG. 101A, the protruded electrode 112 is connected to an interconnection layer 51 formed on a surface of a printed board 50. The protruded electrode 112 and the interconnection layer 51 are connected together mainly through a solder paste 53.
Components of the solder paste 53 are generally adjusted to have a low melting point. More specifically, a ratio of lead (Pb) contained in the solder paste 53 is kept at a low value of about 40%. The amount of lead contained in the solder affects both the fatigue strength and melting point. Although a higher ratio of lead in the solder increases the fatigue strength, it also undesirably increases the melting point. As a result, the ratio of lead in the solder paste 53 is kept at a small value of about 40%.
Referring to FIG. 101B, connection between the protruded electrode 112 and the interconnection layer 51 in this case is effected by the melting of the solder plating layer 115 and the solder paste 53. Components of the connection layer 53b depend on the amount of the components of the solder paste 53. Therefore, the ratio of lead contained in the connection layer 53b is relatively low and is about 40%. This results in a problem that a fatigue strength of the connection layer 53b comes to be small.
Also, a method of manufacturing the first improvement may have following problems. Japanese Patent Laying-Open No. 3-104141 (1991) disclosing the first improvement does not sufficiently disclose the specific manufacturing method. Further, referring to FIG. 96, it is unclear how the semiconductor chip 113 is supported in forming the resin 111.
In order to support the semiconductor chip 113, it is necessary to support the protruded electrodes 112 in an appropriate manner. In connection with this, if the protruded electrode 112 is formed of a single layer of solder, the protruded electrode 112 is soft, so that it may be difficult to fix the same. Further, a barrier layer is not formed between the protruded electrode 112 and the bonding pad 114, so that reliability of the joint between the protruded electrode 112 and the bonding pad 114 may decrease.
Problems of the second improvement will be described below with reference to FIGS. 102A and 102B. In these figures, the protruded electrode 122 in the semiconductor package is electrically connected to the interconnection layer 51 formed on the printed board 50 through the connection layer 53, e.g., of solder paste. Also in this case, the protruded electrode 122 is welded to the solder paste 53 similarly to the case of the first improvement.
As a result, a connection layer 53c is formed in the connection between the protruded electrode 122 and the interconnection layer 51 as shown in FIG. 102B. Components of the connection layer 53c substantially depend on the components of the solder paste 53. Therefore, the fatigue strength of the connection layer 53c between the protruded electrode 122 and the interconnection layer 51 decreases, resulting in low reliability, similarly to the first improvement.
Also a method of manufacturing the second improvement may have following problems. According to the manufacturing method of the second improvement, it is necessary to form the opening 121a in the seal resin 121. The seal resin 121, however, generally contains silica. This makes etching of the seal resin 121 difficult.
More specifically, referring to FIG. 98C, irregularity is liable to be formed in a wall of the opening 121a in forming the opening 121a. Therefore, it is difficult to keep air-tight the seal resin 121 and the protruded electrode 122. It can be considered that wet etching is mainly utilized as an etching technique for forming the opening 121a at present.
In order to form the opening 121a having a predetermined depth, a width of the opening 121a is therefore inevitably increases corresponding to the depth. As a result, it is required to increase a pitch between the openings 121a, so that it is difficult to comply with a demand for increase of pins in number. Since the seal resin 121 is opaque, positioning of the bonding pads 124 and the openings 121a is difficult.
Problems of the third improvement will be described below with reference to FIG. 103. In the operation for connecting the resin seal semiconductor package of the third embodiment to the printed board 50, a flat surface of the semiconductor package including the top surfaces of the electrodes 132 is pressed against the solder pastes which will form the connection layers 53d.
Thereby, the solder pastes spread out and thus may cause short-circuit of the adjacent electrodes 132. More specifically, the connection layers 53d formed of solder pastes contact with the adjacent connection layers 53d as can be seen in regions 55 in FIG. 103. This results in reduction of yield in the connections between the semiconductor package and the printed board 50.
A method of manufacturing in accordance with the third improvement has a problem caused by connecting the electrode 132 to the bonding pad 134, as will be described below. In the manufacturing method of the third improvement, the electrode 132 and the bonding pad 134 may be connected together by directly pressing them together.
For this pressing, a relatively large load is applied for pressing the electrode 132 against the bonding pad 134. As a result, such problems are likely to occur that the bonding pad 134 deforms and that the protection film 136 cracks.
The first and second improvements further have the following problem.
The first and second improvements require the protruded electrodes of about several hundreds microns or more in height. It takes long time to form such protruded electrodes in a conventional method such as a plating method. This reduces productivity.
In the first to third improvements, the protruded electrodes 112, 122, 132 are formed on the bonding pads 114, 124 and 134, respectively. Therefore, the protruded electrodes 112, 122 and 132 can be formed only at the limited positions.
The following problem may occur when the resin seal semiconductor packages of the first to third improvements is mounted on the printed boards. The protruded electrodes 112, 122 or 132 are formed throughout the main surface of the resin seal semiconductor package. When the conventional resin seal semiconductor package is to be mounted on the printed board, the printed board is therefore opposed to the main surface of the resin seal semiconductor package.
Thus, the printed board must have an area nearly equal to the area of the main surface of the resin seal semiconductor package in order to mount the resin seal semiconductor package on the printed board. This restricts high integration of the resin seal semiconductor packages.
The following disadvantage may also be caused in connection with a socket used for evaluating a performance of the resin seal semiconductor packages of the first to third improvements.
FIG. 104 is a perspective view showing an example of a conventional socket used for performance evaluation of the resin seal semiconductor package. Referring to FIG. 104, a conventional socket 203 is provided with contacts 204 to be electrically connected to I/O terminals 202 of a resin seal semiconductor package 201 as well as I/O terminals 205 to be electrically connected to a performance evaluating device (not shown). The I/O terminals 205 are electrically connected to the contacts 204.
In this example, the contact 204 is formed of two metal plate springs. The I/O terminal 202 of the resin seal semiconductor package 201 is inserted between the two metal plate springs of the contact 204. In this state, the performance evaluation of the resin seal semiconductor package 201 is carried out. The socket described above is also used for the screening.
If the socket 203 described above is used for the performance evaluation of the resin seal semiconductor packages having the protruded electrodes 112, 122 and 132 of the first to third improvements, the protruded electrodes 112, 122 and 132 and the contacts 204 cannot ensure stable electrical contact, and thus the socket 203 cannot function satisfactorily.
In connection with the above problems, the following problem also occur if the performance of the resin seal semiconductor packages having the protruded electrodes 112, 122 and 132 of the first to third improvements is to be evaluated with another conventional inspection device. FIG. 105 is a perspective view showing an example of the above another inspection device.
An inspection device 210 having a probe is shown in FIG. 105. The inspection device 210 includes contact needles 213, and also includes first to third screws 216, 221 and 219 for moving the contact needles 213 in a desired direction.
The first screw 216 is used to adjust the position of the contact needle 213 in a vertical direction. The second screw 219 is used to adjust the position of the contact needle 213 in a longitudinal (front to rear) direction. The third screw 221 is used to adjust the position of the contact needle 213 in a lateral (left to right) direction.
The inspection device 210 further includes support bases 220, on which first and second movable bases 217 and 218 are mounted. The contact needle 213 is attached to the first movable base 217 through a support plate 214 and a fixing plate 215.
In an operation for conducting the performance evaluation of the resin seal semiconductor package 211 having the protruded electrodes with the inspection device 210 thus constructed, the first to third screws 216, 219 and 221 are first adjusted appropriately to adjust the positions of the contact needles 213. The contact needles 213 are sequentially brought into contact with the respective protruded electrodes 212 in the resin seal semiconductor package 211. In this manner, the performance evaluation of the resin seal semiconductor package is conducted.
However, the performance evaluation with the inspection device 210 thus constructed requires a time-consuming operation. Further, the inspection device 210 cannot easily ensure stable electrical contact between the contact needle 213 and the protruded electrode 212.